Phase-locked loop (PLL) frequency synthesizers form an important part of devices such as microprocessors, digital signal processors (DSPs), communication systems and other integrated circuit systems. A lock detector typically determines if a PLL output clock signal tracks a reference clock signal. The frequency synthesizer keeps the frequency of the PLL output clock signal locked to some multiple of a reference clock frequency by monitoring the PLL output clock signal.
In a practical integrated circuit (IC), a distribution network such as a clock tree may distribute a PLL output clock signal throughout the IC to receptor circuits that need the PLL output clock signal to properly function. Ideally, the PLL output clock signal should arrive at each receptor circuit in the distribution network without distortion in either frequency or phase as compared with the PLL output clock signal generated at the frequency synthesizer output. However, the PLL output clock signal may pass through many potential bandwidth-limiting blocks before arriving at the receptor circuits as a downstream clock signal. These bandwidth-limiting blocks may include level shifters, clocking buffers in a clocking grid, duty cycle correction circuits, clock multiplexers, pulse width limiters as well as other bandwidth-limiting circuits and devices. Thus, a downstream clock signal that actually reaches a receptor circuit in the distribution network may exhibit a somewhat different frequency and phase than the original PLL output clock signal generated at the frequency synthesizer output. If the frequency of the downstream clock signal varies too much from the frequency of the PLL output clock signal, then frequency lock may be lost and receptor circuits relying on the downstream clock signal may not function properly.
Lock detectors are known that detect when a PLL output signal of a frequency synthesizer exhibits the same frequency as a reference clock signal. One type of lock detector employs two counters. One counter counts the number of reference signal clock pulses and the other counter counts the number of feedback signal pulses. A divider circuit divides the number of PLL output signal pulses to produce the feedback signal. A comparator compares the number of feedback signal pulses with the number of reference clock signal pulses. If the number of feedback signal pulses equals the number of reference clock signal pulses, then the lock detector signals that the frequency synthesizer is locked. While this method determines the existence of a locked state at the immediate output of the frequency synthesizer, it is possible that a locked state may not exist downstream in circuits distant from the immediate output of the frequency synthesizer.
What is needed is a method and apparatus that determines if a downstream clock signal exhibits a frequency lock with respect to a frequency synthesized output clock signal.